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Inference & ServingMedium· Memory Layout· GPU Architecture· Coalescing
Why does column-major access of a row-major matrix perf...
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See plansWhen threads in a warp access a row-major matrix in column-major order, each thread accesses a different row, meaning their memory addresses are separated by the row width. Because each address falls into a different 128-byte burst section, the hardware must issue a separate HBM transaction for every thread. This results in fetching 128 bytes for each thread while using only a small fraction of that data, consuming up to 64x more bandwidth than a coalesced access pattern.